Method for forming metal interconnects in a dielectric material
US8138082B2 · kind B2 · utility
6Cited by
3References
19Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 26, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.