Method for fabricating interconnect structures for semiconductor devices
US8143138B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Dec 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.