Non-volatile memory cell with self aligned floating and erase gates, and method of making same

US8148768B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Nhan Do · Saratoga, US
• Amitay Levi · Cupertino, US

Key dates

• Filing date: Nov 26, 2008
• Grant date: Apr 3, 2012
• Expiry date: Jun 15, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. The erase gate includes a notch, and the floating gate includes an edge that directly faces and is insulated from the notch.