Method to compensate optical proximity correction
US8151221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2010 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Sep 25, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a region except the active regions. The IC layout further includes ion implant regions which are overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Each photoresist line width compensation region is disposed in the STI region. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Finally, the corrected IC layout is transferred to a photomask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.