Method of forming metal/high-κ gate stacks with high mobility
US8153514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2008 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Dec 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.