Dual-leadframe multi-chip package and method of manufacture
US8154108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2010 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacitor configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.