Yield enhancement for stacked chips through rotationally-connecting-interposer
US8159247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jul 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.