Chaining multiple smaller store queue entries for more efficient store queue usage
US8166246B2 · kind B2 · utility
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4References
13Claims
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Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.