Enhanced architectural interconnect options enabled with flipped die on a multi-chip package

US8174103B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gerald K. Bartley · Rochester, US
• Darryl J. Becker · Rochester, US
• Paul Eric Dahlen · Rochester, US
• Philip Raymond Germann · Oronoco, US
• Andrew Benson Maki · Rochester, US
• Mark O. Maxson · Mantorville, US

Key dates

• Filing date: May 1, 2008
• Grant date: May 8, 2012
• Expiry date: Jul 15, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.