Drive current adjustment for transistors by local gate engineering

US8188871B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Manfred Horstmann · Dresden, DE
• Patrick Press · Dresden, DE
• Karsten Wieczorek · Dresden, DE
• Kerstin Ruttloff · Frankenberg/Sachsen, DE

Key dates

• Filing date: May 27, 2009
• Grant date: May 29, 2012
• Expiry date: May 24, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.