PLD architecture for flexible placement of IP function blocks
US8201129B2 · kind B2 · utility
8Cited by
162References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | May 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.