Methods for forming a memory cell having a top oxide spacer

US8202779B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Shenqing Fang · Fremont, US
• Angela T. Hui · Fremont, US
• Gang Xue · Beijing, CN
• Alexander H. Nickel · San Jose, US
• Kashmir Sahota · Fremont, US
• Scott A. Bell · San Jose, US
• Chun Chen · San Jose, US
• Wai Lo · Sha Tin, CN

Key dates

• Filing date: Sep 27, 2010
• Grant date: Jun 19, 2012
• Expiry date: Sep 27, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.