Method of forming vias in silicon carbide and resulting devices and circuits
US8202796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2011 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.