Reducing effects of erase disturb in a memory device
US8203876B2 · kind B2 · utility
9Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Apr 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.