Patent · US Active

Method and apparatus for reducing semiconductor package tensile stress

US8212346B2 · kind B2 · utility

2Cited by

11References

9Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

E. Todd Ryan · Clifton Park, US
Holger Schuehrer · Dresden, DE
Seung-Hyun Rhee · Fishkill, US

Key dates

Filing date	Oct 28, 2008
Grant date	Jul 3, 2012
Priority date	—
Expiry date	Nov 16, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/12044
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.