Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
US8212353B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Aug 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.