Method of forming a packaged semiconductor device
US8216918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2010 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Jul 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1469
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.