Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
US8217463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2011 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Feb 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.