System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) with routing model
US8219341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2009 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Mar 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.