Patent · US Active

Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source select gate

US8228735B2 · kind B2 · utility

15Cited by

4References

21Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Giuseppina Puzzilli · Boise, US
Andrew Bicksler · Nampa, US
Akira Goda · Boise, US

Key dates

Filing date	Feb 17, 2010
Grant date	Jul 24, 2012
Priority date	—
Expiry date	Dec 24, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/0483
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.