Forming a non-planar transistor having a quantum well channel
US8237153B2 · kind B2 · utility
9Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2011 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Mar 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/47
Abstract
In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.