Semiconductor device and method of forming wafer level multi-row etched lead package
US8241956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Dec 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.