Method of integrating a MOSFET with a capacitor
US8247288B2 · kind B2 · utility
4Cited by
0References
23Claims
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Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.