Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack
US8247850B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Sep 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.