Ross E. Noble
6Patents
2h-index
11Co-inventors
44Inventor score
Filing activity: Sep 15, 2003 → Jul 20, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6908822B2 | Semiconductor device having an insulating layer and method for forming | Electricity | 21 | Expired |
| US8039386B1 | Method for forming a through silicon via (TSV) | Electricity | 4 | Active |
| US8247850B2 | Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack | Electricity | 2 | Active |
| US7972922B2 | Method of forming a semiconductor layer | Emerging Cross-Sectional Technologies | 1 | Active |
| US7611936B2 | Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method | Electricity | 1 | Active |
| US11162683B1 | Self-stoking combustion appliance and cookers | Mechanical Engineering; Lighting; Heating | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.