Fabrication of through-silicon vias on silicon wafers
US8283237B2 · kind B2 · utility
8Cited by
18References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Dec 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.