Dual die semiconductor package
US8288847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Oct 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.