Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction
US8293544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2008 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Feb 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/105
Abstract
A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.