Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)

US8293605B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Peter Baars · Dresden, DE
• Marco Lepper · Dresden, DE
• Clemens Fitz · Dresden, DE

Key dates

• Filing date: Feb 25, 2011
• Grant date: Oct 23, 2012
• Expiry date: Feb 25, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.