Patent · US Active

Semiconductor device comprising a metal gate stack of reduced height and method of forming the same

US8293610B2 · kind B2 · utility

2Cited by

7References

18Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Sven Beyer · Dresden, DE
Rolf Stephan · Dresden, DE
Martin Trentzsch · Dresden, DE
Patrick Press · Dresden, DE

Key dates

Filing date	Sep 4, 2008
Grant date	Oct 23, 2012
Priority date	—
Expiry date	Sep 18, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/691

Abstract

By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.