Sub-field enhanced global alignment

US8299446B2 · kind B2 · utility

Assignee

• Ultratech · US

Inventors

• Andrew M. Hawryluk · Los Altos, US
• Emily True · Pleasanton, US
• Manish Ranjan · Sherwood, US
• Warren W. Flack · San Jose, US
• Detlef Fuchs · Folsom, US

Key dates

• Filing date: Jun 24, 2010
• Grant date: Oct 30, 2012
• Expiry date: Jul 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.