Patent · US Active

Structure for electrostatic discharge in embedded wafer level packages

US8309454B2 · kind B2 · utility

8Cited by
5References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 10, 2007
Grant dateNov 13, 2012
Priority date
Expiry dateSep 16, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3025
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.