Thin stacked interposer package
US8319338B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jun 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.