Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices
US8323989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.