Patent · US Active

Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition

US8324091B2 · kind B2 · utility

0Cited by

3References

24Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Joachim Metzger · Rockenberg, DE
Robert Binder · Dresden, DE
Markus Lenski · Dresden, DE
Klaus Hempel · Dresden, DE

Key dates

Filing date	Feb 24, 2010
Grant date	Dec 4, 2012
Priority date	—
Expiry date	Dec 15, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/691
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.