Victim cache replacement
US8327072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2008 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core, the lower level cache victim determines whether the memory access request hits or misses in the directory of the lower level victim cache, and the upper level cache determines whether a castout from the upper level cache is to be performed and selects a victim coherency granule for eviction from the upper level cache. In response to determining that a castout from the upper level cache is to be performed, the upper level cache evicts the selected victim coherency granule. In the eviction, the upper level cache reads out the victim coherency granule from the data array of the upper level cache only in response to an indication that the memory access request misses in the directory of the lower level victim cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.