Fabrication of through-silicon vias on silicon wafers
US8329575B2 · kind B2 · utility
3Cited by
18References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.