Reconfigurable memory arrays having programmable impedance elements and corresponding methods
US8331128B1 · kind B1 · utility
40Cited by
39References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.