Semiconductor device containing a buried threshold voltage adjustment layer and method of forming
US8334183B2 · kind B2 · utility
2Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.