Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US8334584B2 · kind B2 · utility
8Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a base array having terminals and an open region; attaching a coverlay layer directly on the base array; placing a component in the open region and directly on the coverlay layer; forming an encapsulation over the base array and the component; removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed and substantially coplanar; and removing a portion of the base array between the terminals, the terminals electrically isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.