Stress mitigation in packaged microchips
US8344487B2 · kind B2 · utility
19Cited by
89References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jul 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.