Patent · US Active

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

US8349694B2 · kind B2 · utility

8Cited by

0References

18Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Stephan Kronholz · Dresden, DE
Markus Lenski · Dresden, DE
Andy Wei · Queensbury, US
Martin Gerhardt · Dresden, DE

Key dates

Filing date	Oct 21, 2010
Grant date	Jan 8, 2013
Priority date	—
Expiry date	Oct 21, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0186
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.