Patent · US Active

Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection

US8354316B2 · kind B2 · utility

2Cited by

0References

10Claims

0Family size

Inventors

Anup Bhalla · Santa Clara, US
Xiaobin Wang · Chanhassen, US
Wei-Chuan Wang · Hamburg, DE
Yi Su · Sunnyvale, US
Daniel Ng · Campbell, US

Key dates

Filing date	Oct 29, 2010
Grant date	Jan 15, 2013
Priority date	—
Expiry date	Oct 29, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/112

Abstract

A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.