Method for fabricating semiconductor devices with reduced junction diffusion
US8354321B2 · kind B2 · utility
4Cited by
2References
20Claims
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Key dates
| Filing date | Oct 19, 2011 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Oct 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6758
Abstract
A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.