Integrated circuit package and a method for forming an integrated circuit package

US8357565B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gerald Ofner · Regensburg, DE
• Swain Hong Yeo · Singapore, SG
• Mary Teo · Singapore, SG
• Pei Siang Lim · Singapore, SG
• Khoon Lam Chua · Singapore, SG

Key dates

• Filing date: Oct 1, 2010
• Grant date: Jan 22, 2013
• Expiry date: Oct 1, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/01078
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture.