Non-volatile memory unit cell with improved sensing margin and reliability
US8363475B2 · kind B2 · utility
1Cited by
3References
9Claims
0Family size
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Key dates
| Filing date | Mar 30, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Feb 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.