Patent · US Active

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

US8367495B2 · kind B2 · utility

5Cited by

2References

20Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Sven Beyer · Dresden, DE
Markus Lenski · Dresden, DE
Richard J. Carter · Los Altos, US
Klaus Hempel · Dresden, DE

Key dates

Filing date	Mar 29, 2010
Grant date	Feb 5, 2013
Priority date	—
Expiry date	Feb 12, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/01
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.