Compact field effect transistor with counter-electrode and fabrication method
US8368128B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 3, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jun 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.