Patent · US Active

Fused buss for plating features on a semiconductor die

US8368172B1 · kind B1 · utility

2Cited by

6References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

George R. Leal · Cedar Park, US
Kevin J. Hess · Austin, US
Trent S. Uehling · Austin, US

Key dates

Filing date	Jul 22, 2011
Grant date	Feb 5, 2013
Priority date	—
Expiry date	Jul 22, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/02166
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.