Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode
US8373208B2 · kind B2 · utility
13Cited by
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14Claims
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Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.